The present invention relates to the mounting of solid-state imager chips in an optical assembly and preferably to the mounting of solid-state imager chips having a thinned semiconductor substrate.
In general, a plurality of individual solid-state imagers, such as charge-coupled devices (CCD's), are fabricated by the selective doping in and the depositing of an electrode structure on what is conventionally called the gate side of a relatively thick (e.g. approximately 12-15 mils) semiconductor wafer. The wafer is then cut-up by a process called "dicing" for separating the individual imagers into imager chips. The electronic devices formed in the imager chips by these conventional techniques create photosensitive picture elements (pixels) which develop charges in potential wells in the semiconductor substrate beneath the electrode structure which are representative of radiant energy, such as visible light, directed at the pixels when a scene is optically imaged thereon. The charges are subsequently read-out of the pixels for developing electrical signals representative of the scene. With such imager chips, radiant energy is directed at the pixels from the gate side of the imager chip and must therefore pass through the chips electrode structure (i.e., some energy passes through the spaces between electrodes and some energy actually passes through the electrodes). Although the electrodes are thin enough to pass some visible light, the imager's responsitivity to shorter wavelengths of visible light is reduced when the light passes through the electrodes, especially its responsitivity to blue light. Additionally, the electrode structure blocks some light, reducing sensitivity.
In order to improve imager responsitivity and sensitivity, imagers have been developed wherein the side of the semiconductor substrate opposite the gate side is thinned, e.g., by chemical etching, to about 8-10 micrometers. FIG. 1a illustrates an imager chip 10 having a thinned semiconductor substrate. With a thinned substrate imager, radiant energy can be directed at the pixels from the thinned substrate side. The radiant energy develops electrons which are collected in the substrate's potential wells formed beneath the electrode structure. Since the radiant energy does not have to pass through and/or around an electrode structure, a thinned substrate imager is more responsive to visible light than the previously described thick substrate imager. For providing structural integrity to the thinned substrate imager, a relatively thick piece of glass (e.g., 10-20 mils) is uniformly bonded to the thinned substrate using an optical quality adhesive for forming a laminated structure. Details of a method for the manufacture of such thinned substrate imager chips is disclosed in U.S. Pat. No. 4,266,334 issued May 12, 1981 to Edwards and Pennypacker and assigned, like the present application, to RCA Corporation.
The conventional packaging of such thinned substrate imagers and the mounting of such packages to, e.g., a light splitting prism 100 (of a color video camera, not shown) is illustrated by the section and top views of an IC (integrated circuit) package 110 shown in FIGS. 1b and 1c, respectively. Package 110 includes an electrically insulating ceramic chip carrier 112 having an opening 114 and an interior shoulder portion 116 aligned with opening 114. Shoulder portion 116 supports thinned-substrate imager chip 10 such that light entering opening 114 falls on the thinned substrate side of imager chip 10. The glass laminate 120 of imager chip 10 is epoxied at its periphery to shoulder 116 so as to not interfere with the passage of light to chip 10. A glass window 122 is epoxied at its periphery to the carrier portion opposite shoulder 116, for protecting imager 10 from dirt and other contaminants while allowing light passage to imager chip 10. Electrical connection of external drive and signal processing circuitry (not shown) to imager chip 10 is made by bonding wires 124 from the gate side of imager chip 10 to a metallization pattern (not shown) formed in carrier 112, which in turn is connected to connector pins 126. The drive and signal processing circuitry are connected by conventional printed circuit board techniques to pins 126. An opaque lid 128 completes IC package 110 and is expoxied to the side of carrier 112 which is opposite window 122, for hermetically sealing and preventing extraneous light from entering IC package 110.
The positioning and mounting of IC package 110 to prism 100 may be in accordance with the teachings in U.S. Pat. No. 4,268,119 issued to Hartmann on May 19, 1981, which teaches the use of a rectangular gasket 130 having a generally rectangular opening therethrough approximately the size and shape of window 122. Preferably, gasket 130 is formed of a flexible, foamed body of material such as foam rubber and dimensioned to be in surrounding contact with window 122 of IC package 110 and in contact with an exit port 132 of prism 100. Next, mechanical micromanipulators (not shown) grasp IC package 110 and its position is precisely located in X, Y and Z planes, such that the imaging plane of imager chip 10 is e.g., the proper distance from, paralleled to and centered with respect to the optical access of exit port 132. It should be noted that the parallelness of the plane of the imaging area of the chip with the plane of the window 122 may be adversely affected by uneven application of adhesive when attaching the imager chip within package 110. Additionally, imager chip 10 must be without rotation relative to other detectors (not shown) mounted at other exit faces (not shown) of prism 100 such that the raster of imager representative signals supplied from the imager chip 10 is in registry with the image representative signals supplied from the other imagers when viewed on a monitor.
Once IC package 110 has been correctly positioned with respect to exit port 132, an adhesive or hardening cement, such as epoxy is applied around gasket 130 or injected thereinto so as to impregnate gasket 130 while IC package 110 is held in position. Thus, after the epoxy hardens it forms a rigid body which provides a secure bond between package 110 and prism exit port 132.
It should be noted that imager chip 10 is supported in IC package 110 in a manner such that its position is not precisely the same from IC package to IC package. That is, since shoulder portion 116 of carrier 112 is larger than imager chip 10, the position of chip 10 within shoulder 116 is not precisely determined and can vary during manufacture. Additionally, the parallelness of the imaging plane of imager chip 10 to window 122 can vary during manfacture due to uneven application of adhesive about the peripheries of either one or both of window 122 and imager chip 10. Thus, the above described positioning and mounting procedure must be performed for each IC package to be mounted to an optical assembly, such as the exit ports of prism 100.
FIG. 2 illustrates a package 210 for an imager chip 200 having a relatively thick semiconductor substrate 202. Package 210 includes a carrier 212, pins 226 and bonding wires 224 similar to package 110 of FIG. 1b, except that since imager chip 200 is illuminated from its gate side (because semiconductor substrate 202 is too thick to pass light), carrier 212 does not require an opening in its recessed portion 216. Thus, substrate 202 of imager 200 is epoxied in recess 216 of carrier 212 and a glass window 222 is epoxied about its periphery to carrier 212 for hermetically sealing the package while allowing light to pass through to the pixels formed on the gate side of imager chip 200. Package 210 may be mounted to prism 100 in substantially the same manner as the previously described mounting for IC package 110, such that window 222 is positioned to face the exit port of prism 100.
It is herein recognized that IC packages such as described above for solid-state imager chips are undesirable for a variety of reasons. Firstly, as previously noted, the imager chip may not be located in its IC package in a precise location during manufacture, resulting in chip location variations from IC package to IC package. Thus, rather cumbersome mounting techniques, such as the use of a resilient foam gasket are required for taking these imprecise chip locations into account when mounting an IC package, such that its imaging area is parallel and precisely located with respect to e.g., an exit port of a prism. Secondly, although the glass window protects the photosensitive surface of the imager chip from dirt, etc. from outside sources, particles such as flakes of adhesive and the like can come loose inside the package over a period of time and fall onto the photosensitive surface of the imager, causing imaging defects. Thirdly, the recessing of the imager can cause vignetting (a gradual shading at the image edges so as to leave no defined line at the border) of the image, especially in package 110, due to opening 114. Fourthly, the gap between the imager and the glass window of the package creates a space where condensation can form and degrade the image. Additionally, there are structural integrity and thermal stability problems associated with package 110 since, imager 10 is only supported by epoxy around its periphery. Finally, and perhaps more importantly, as manufacturing techniques improve and imager yields increase, the cost of the imager chip decreases to the point where the cost of the imager chip package becomes a significant part of the expense of a packaged imager. Therefore, it is herein recognized that it is desirable to eliminate the above-noted disadvantages of solid-state imager packages.